1. Field
This disclosure relates to a single poly non-volatile memory device, and more particularly, to a single poly non-volatile memory device and a method of manufacturing and arranging the same that improve operation efficiency and reduce an area by disposing a sensing transistor and a selection transistor at one well and a control gate at another well.
2. Description of Related Art
A non-volatile memory device may be referred to as a Non Volatile Memory (NVM) and can stably store data for a long period without power. Representative nonvolatile memory devices include flash memory device and an Electrical Erasable Programmable Read-Only Memory (EEPROM) devices. An EEPROM can electrically erase and restore data stored therein through conversion of an erasable programmable read-only memory (EPROM). Therefore, the non-volatile memory device is conveniently used in an application field requiring to restore a program and may store or erase data by electrically changing electric charges of an element constituting a chip. Because the non-volatile memory device can electrically read or store data, the non-volatile memory device may be programmed again in a state embedded in a system and is thus used in an application field requiring information change of a user.
In general, an EEPROM uses a double poly structure that stacks two polys or a single poly structure using one poly, and the present invention relates to a single poly non-volatile element using one poly. The single poly non-volatile element may be formed without a separate high voltage process or high voltage element using a method of applying +VPP and −VPP upon performing a program or erase operation. That is, by changing a medium voltage device to a single poly non-volatile memory device without a high voltage process or a high voltage element and by constituting a circuit with the medium voltage device, the single poly non-volatile element may be compatible with a logic process. Thereby, there is a merit that a production step reduces and thus a cost reduces and a production time is shortened.
In a conventional single poly non-volatile memory device, a tunneling area and a sensing transistor are implemented in a separated structure to increase an area of a memory cell. Further, in the conventional art, the sensing transistor is disposed at a periphery of a source electrode, and by a depletion area according to PN junction, a substantial tunneling area reduces. That is, in the conventional art, upon performing an erase operation, by reducing the number of electrons injected or discharged through the sensing transistor, there is a problem that efficiency of the erase operation reduces.